IP100A LF-DS-R17 Technical Datasheet

Description Single chip 10/100BASE, half or full duplex The IP100A LF is a single-chip, full duplex, Ethernet Media Access Controller 10/100Mbps Ethernet MAC + PHY incorporating a IEEE 802.3 compliant 32-bit PCI with bus master support. The IP100A 100BASE-TX/100BASE-FX/10BASE-T LF is designed for use in a variety of applications PCI Bus master scatter/gather DMA on any including workstation NICs, PC motherboards, byte boundary and other systems utilizing a PCI bus that require Full operation with PCI Clock from 25 MHz to network connectivity to an Ethernet or Fast 33 MHz Ethernet LAN. PCI Revision 2.2 compliant On-chip transmit and receive FIFO buffers The IP100A LF includes a PCI bus interface unit, On-chip LED drivers IEEE 802.3 compliant MAC, transmit and receive Power management capabilities for ACPI 1.0 FIFO buffers, IEEE 802.3 compliant 100BASE-TX, compliant systems 10BASE-T, and 100BASE-FX PHY, serial WakeOnLAN support EEPROM interface and LED drivers. Management statistics gathering IP multicast recei